There are obviously outliers in both directions. Both the cost and the duration are typically proportional to the size of the effort. We’re not hobbyists.
Here are some general examples:
PCB Layout Services with optional Signal Integrity analysis and optimization
~$15K to $100K
~ 1 to 8 weeks
Low to medium complexity microcontroller-based boardschematic design & PCB layout and firmware development
~$50K to $125K
~ 6 to 12 weeks
Schematic and/or PCB Layout peer review (w/ summary of analysis and findings report)
~$10K to $25K²
~ 1 to 3 weeks
System EMC assessment (w/ summary report including root cause analysis and recommended countermeasures)
~$15K to $50K
~ 1 to 4 weeks
Semi Custom Mechanical Enclosure Design (Customization of off the shelf enclosure) in parallel with board design
~$7K to $15K
~2 to 12 weeks
Phase 0 – Requirements generation, architecture, analysis of alternatives, cost estimation (for a typical medium-complexity system)
~$15K to $50K ³
~1 to 2 weeks
¹ FPGA development has a very wide range of complexity of implementation and test benching. This estimate falls into 80% of the projects Re:Build AppliedLogix works on.
² Printed Circuit Boards can range from simple 2- to 4-layer boards for interconnects or IoT devices to very complicated 30+ layer backplanes transferring terabits of data per second.
³ Phase 0 efforts are critical to many programs’ success to ensure de-risking and scope alignment happens at the onset of a project vs later when it is more expensive to pivot.
My appreciation to the AppliedLogix folks for pulling this one out of the fire… This is going to be big – you can’t believe the response. Product is dead-on for first generation.
Program Manager, Wireless Biometrics Monitoring Product Manufacturer
A.L.’s capacity to frame and follow through on complex assignments is frighteningly good! I wish I could say it’s just youthful energy but you guys aren’t that young either. It’s very valuable.
Principal System Architect, Engineering Consultancy for Energy Industry
The new layout for the AVDD power planes is excellent – great job of maximizing the clearance to critical input nodes… Very well thought out and executed… You should be proud of this work!
Ultrasound Expert, Research University
…There are many high power / high current PWM channels and the critical low noise signals are perfectly quiet, there is no discernible noise at all. The layout is extraordinary – well done AppliedLogix!
Product Engineering Manager, Alternative Energy Power Systems
Let’s talk about your unique challenges and how Re:Build AppliedLogix can help you.
