FPGA Development

Delivering FPGA-based Solutions

With over 100 FPGA-based solutions delivered to our customers, our approach covers every aspect of development. From initial whiteboard concepts to rapid prototypes and full production, we excel in Requirements Capture and Architectural Planning. Our expertise extends through RTL Capture and Build, while our rigorous Verification, Integration, and Debug processes ensure top-notch quality. Supported by robust Version Control and Scripting, we bring ideas to life with efficiency and precision at every stage.

Requirements Capture and Architectural Planning

We collaborate closely with clients and other designers (hardware and software) to identify and mitigate risks early. Our experience helps clients choose the right device and footprint for their current design and budget, while also considering their future plans.

RTL Capture and Build

Constraint-based design allows us to create complex custom solutions while minimizing risk. With multi-clock-domain designs becoming standard, we excel at coding and properly constraining domain crossings, ensuring our designs consistently meet timing requirements. We are adept at engineering FPGA designs that close timing accurately, even under budget and size constraints, achieving over 75% fabric utilization and operating at over 75% of the rated maximum frequency.

Verification, Integration and Debugging

Module-level and top-level testbenches are deployed to thoroughly test a design and provide error reports, while scripted regression testing provides a verification of design changes comprehensively. High-risk interfaces are mitigated early using development boards whenever possible. Our experience includes hardware-in-loop (HIL) testing, in-fabric logic analyzers, and custom pattern generators, all contributing to our emphasis on designing for testability.

Version Control and Scripting

We utilize internal Git repositories or the client’s own repository for version control, and extensively employ scripting for project recreation, build automation, and regression testing.

FPGA Design Experience

RTL and testbench languages: VHDL(-2008), Verilog, and SystemVerilog
Development tools: Intel Quartus, AMD Vivado, Xilinx ISE, Lattice Diamond, ModelSim, Riviera-PRO, Active-HDL, MATLAB HDL Coder / Simulink
Multi-gigabit high-speed serial transceivers: PCIe, Aurora, SFP, QSFP, custom
SERDES channel verification with S-parameter extraction and IBIS-AMI-based margin analysis

MicroBlaze and NIOS-II soft processor core applications
Zynq Ultrascale+ and Zynq 7000 SOC applications
Internal/external interfaces: SPI, I2C, Ethernet 10M/100M/1G/10G, I2S, CAN, PCIe, Avalon-MM, Avalon-ST, AMBA AXI4, AMBA AXI4-Lite, AMBA AXI4-Stream, MIPI, CSI, LVDS, CML

Design and package custom IP core
Hardware debug: Vivado ILA/VIO, Quartus SignalTap
Remote updates via in-field re-programmability

Solutions

Our expertise spans a wide range of capabilities, including still image and video capture and processing, with advanced DSNU and PRNU corrections. We generate real-time, industry-standard image file formats within the fabric, and our motion control solutions provide precise motor speed and position monitoring. Precision timing is critical for image sensor control, ADC sampling, and system-level synchronization. We excel in sensor interfacing, managing control and data capture for high-speed CMOS and CCD image sensors, and high-speed DACs and ADCs, including JESD204B and MIPI-CSI standards. Our digital signal processing solutions encompass data buffering, re-assembly, FIR filters, FFTs, DDC, and DDS. Additionally, we implement high-performance DDRx memory, including DDR4 at 1.2 GHz, and develop safety-critical logic for robust and reliable performance.

We have extensive development experience with various SoC, FPGA, and CPLD device families, which include:

AMD/Xilinx

Zynq-7000
Zynq-UltraScale+
MPSoC UltraScale+
RFSoC UltraScale+
Artix-7
Artix UltraScale+
Kintex-7
Kria SOM

Intel/Altera

Cyclone V SoC
Arria V SoC
Arria 10 SoC
Stratix 10 SoC
Agilex 7

Lattice

ECP5