Why You Should Consider FPGA-in-the-Loop Testing

Traditional FPGA development flow can be a time-consuming process. Time spent in each of the design, implementation, and testing phases accumulates as the cycle repeats.  Simulation, both setup and runtime, takes a tremendous amount of time as the size of the design increases, to the point where it may not be feasible to run a formal simulation to test every change. Furthermore, simulation results aren’t always indicative of the design’s behavior in actual hardware.

That’s where FPGA-in-the-loop (FIL) testing can help.

FIL is a form of hardware-in-the-loop testing where the load or device under test is an FPGA. It sits right at the intersection of simulation and real hardware testing.

In a typical FIL setup, the FPGA is connected to a host computer, often running an environment like MATLAB/Simulink, via JTAG or a high-speed communication link (like Ethernet or PCIe). The host computer runs the simulation testbench, which includes the stimuli (inputs) and the analysis (outputs). Instead of the testbench sending the stimuli to a software model of the FPGA, it sends them directly to the physical FPGA hardware. The FPGA processes the data in real-time and sends the results back to the host computer for verification and analysis. This connection allows you to use the sophisticated, high-level control and data analysis capabilities of the software environment while executing your logic on the actual target hardware.

While it doesn’t replace traditional forms of design verification, it offers several advantages.

1. Get results from real hardware – With reliable hardware operation being the goal, the typical design cycle includes simulation to validate a design. However, most FPGA developers have experienced a situation where design validation passes in simulation but not in hardware. Such scenarios call for debugging the problem in hardware.  FIL offers a controlled approach to identify the root cause of hardware behavioral issues. 
2. Enable earlier design validation – FIL provides huge benefits during early development. Whereas traditional IP core development and verification rely on time-consuming simulation, FIL leverages a quick-building FPGA bitstream and runs on actual hardware, providing valuable insights on real-world performance and power consumption.
3. Reduce simulation time – FIL can save time in the design and test cycle of an IP core by integrating the modeling and testing workflows into one common workflow. A MATLAB model integrates into a Simulink testbench for quick validation and may be substituted with an FPGA implementation of the MATLAB model directly within Simulink.  Not only is this a flexible environment – its reuse of the Simulink testbench eliminates the need to develop a separate HDL simulation environment.
4. Achieve controllable stimulus injection – Injecting a repeatable stimulus into an FPGA is a common challenge. Simulation provides the most control over the stimulus to the system, especially with more complex stimuli.  FIL leverages simulation’s high degree of stimulus control for better hardware testing.  This can be especially powerful for identifying and replicating behavioral anomalies and corner cases, leading to a much more robust FPGA design.
5. Faster design cycle – Some FPGA vendors offer a distinct advantage by integrating MATLAB support into their design suite. Altera’s DSP Builder enables a rapid transition between prototyping, implementing, and testing a digital filter by generating an HDL implementation from an imported MATLAB algorithm.  For AMD/Xilinx-based designs, the Vitis Model Composer application generates FIL-supporting IP cores and a MATLAB testbench, streamlining the design-implement-test flow even further.

When to Use FIL vs. Traditional Simulation

While FIL is a powerful tool, it does not completely replace HDL simulation. Knowing when to use each method is key to an efficient design flow.

• Use HDL Simulation (Verification):
  • For verifying all corner cases and timing requirements within a few clock cycles or microseconds of simulation time, HDL simulation is essential. HDL simulators provide cycle-accurate visibility into every signal and register, which is crucial for deep functional debugging, especially during early unit-level verification.
  • A developer should use HDL simulation when the design is highly complex or early in development, requiring rapid iteration on code changes before the synthesis and implementation overhead.
  • Use this method for running long, highly specific test sequences that are too time-consuming to transfer over the host-FPGA communication link (though this is mitigated by pre-loading data into on-chip memory).
• Use FPGA-in-the-Loop (Validation):
  • FIL is necessary when your test requires the actual, physical timing and resource constraints of the target device to be accurately modeled.
  • Consider FIL for running long test vectors (seconds or minutes of real-time data) that would take hours or days to complete in an HDL simulator. This is often the case for testing algorithms like complex communication protocols or large image/video processing pipelines.
  • The designer should also use FIL when they need to integrate the design with external, physical components (e.g., a real ADC/DAC or external sensor) that cannot be easily modeled in software simulation. FIL can often be extended into true HIL testing.

Essential Components of an FIL Setup

Understanding the necessary components can help a developer plan their testing infrastructure. A functional FIL setup typically requires the following:

• Host Computer: Runs the modeling and simulation software (e.g., MATLAB/Simulink). This is where the test vector generation, data logging, and result comparison happen.
• FPGA Development Board: The physical hardware that contains the target FPGA chip, which holds the design implementation. This board often includes necessary interfaces (like external memory or ADCs/DACs) for real-world interaction.
• FPGA-to-Host Communication Link: This is the critical bridge that transfers input stimuli and output results between the host computer and the FPGA. Common interfaces include Ethernet, JTAG, PCIe, or proprietary links like a high-speed USB. The selection of this link often dictates the data throughput and latency of the test.
• HDL Code Generation Tool: Software that automatically translates the high-level model (e.g., in Simulink) into a hardware description language (HDL) like VHDL or Verilog and then generates the necessary bitstream for the FPGA.
• FIL Interface Blocks/IP: These are specialized blocks (often provided by the vendor) that handle the communication protocol on both the host (software) and FPGA (hardware) sides, ensuring seamless data exchange.

Discuss Your FPGA Challenges

Successfully integrating the necessary hardware and software components can introduce new challenges related to communication protocols, toolchain compatibility, and high-speed data transfer.

Are you facing bottlenecks with long simulation times or struggling to replicate hardware anomalies? Our team specializes in customizing FIL workflows to fit unique, large-scale FPGA projects. We can help you leverage these advanced testing techniques to your goals.

Fill out the form below and someone from our engineering team will reach out about a personalized consultation.